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Description: the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
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Size: 1024 |
Author: prabakaran |
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Description: Tcode is in VERILOG HDL (Hardware description language)
code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language)
code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
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Size: 1024 |
Author: hassan |
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Description: 用verilog实现串行口UART控制器,适用于XILINX器件-verilog UART controller
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Size: 343040 |
Author: bigchop ma |
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Description: RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
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Size: 79872 |
Author: cuiqiang |
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Description: 自己写的Verilog写的串口程序,实现收发功能。方法不错,可以参考下。-verilog...uart...
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Size: 538624 |
Author: 地主 |
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Description: RS232(UART)串口传输,通过了FPGA验证功能正确-UART RS232 verilog HDL
FPGA xilinx
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Size: 237568 |
Author: 徐 |
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Description: UART Verilog,书中里的例子,绝对正确,用Verilog语言编写的串口通信例子-UART VerilogCommand Parsing NiosII serial serial parts, including the interruption, send the command prompt, receiving treatment and other characters. Spent a lot of hard work! Definitely useful for beginners
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Size: 4096 |
Author: 李燕乐 |
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Description: a UART model with FIFO buffer, design with verilog
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Size: 145408 |
Author: quang |
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Description: Implementation of the UART 16550 model with verilog langugue
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Size: 40960 |
Author: quang |
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Description: SPI的Verilog实现(非常的全面和详细,还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
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Size: 8192 |
Author: 尚林 |
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Description: uart 收发器 verilog 代码,实现自收发功能
sys clk = 25m, baud 9600 停止位1, 无校验位;
代码实现了串口自收发功能,及把从 PC 收到的内容都发送会 PC, 其他波特率,自行修改代码即可,在 alter 的FPGA 上调试通过; -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
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Size: 2048 |
Author: 周西东 |
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Description: It s combination logic for UART. Edited in verilog-HDL.
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Size: 5120 |
Author: kim |
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Description: uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
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Size: 36864 |
Author: thegreeneyes |
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Description: UART With Verilog
Unit for Transmission
Unit for Reception
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Size: 93184 |
Author: Rami |
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Description: FPGA的UART程序,非常好的,讲解详细,我当初看了好多都看不懂,看了这个以后终于明白-FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this
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Size: 276480 |
Author: xuxing |
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Description: 这是一个uart串口实现16550的实现,代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
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Size: 35840 |
Author: wangli |
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Description: 用verilog语言编写uart程序。模拟串口时序进行收发数据操作。-verilog uart
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Size: 313344 |
Author: 一贯故 |
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Description: 通用异步通讯UART的工程文档,ISE打开工程,里面有VERILOG的源代码,可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
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Size: 30720 |
Author: mike |
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Description: verilog 串口模块,高度集成,下载下就能用-verilog uart communication,easy use
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Size: 31744 |
Author: zyy |
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Description: xilinx官网提供的VHDL,UART串行通信模块,肯定好用,官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
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Size: 10240 |
Author: 雪尘 |
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